FPGA Design Verification Engineer [rekrutacja online]

FPGA Design Verification Engineer [rekrutacja online]
Miejsce pracy: Kraków

Daily activities
 

As part of our team you will contribute to requirements analysis and decomposition, design and implement the verification scenarios using System Verilog and UVM of new FPGA functionalities for 5G telecommunication system following the complete end to end project life cycle.

You will develop extensive knowledge of 5G system physical layer, Nokia hardware platforms and the way our customers are deploying them. You will contribute to develop innovative solutions to address Nokia strategy in the 5G domain and beyond.

 

We work with:
  • System Verilog, UVM.
  • Git.
  • Python.
  • Linux.
  • Testing frameworks.
  • JIRA.
  • Version control and code review systems.
  • Continuous integration systems.
Our expectations:
  • Education: gained BSC / Engineer in: Telecommunication, Computer Science, Electronics or a similar subject.
  • Good knowledge of English (both spoken and written).
  • FPGA programming or willingness to learn - verification skills: System Verilog, UVM.
  • Experience in FPGA verification and integration or objective programming (minimum 2 years of commercial experience).
  • Understanding of technical documentation and technical writing skills.
  • Good mathematical skills.
  • Low level/platform programming & debugging tools knowledge is an advantage.
Nice to have:
  • Verilog/VHDL knowledge.
  • Telecommunication knowledge is an advantage.
  • Embedded system background knowledge is an advantage.
  • Good programming skills with script languages (e.g. Python, Perl, Tcl) is an advantage.
  • Matlab/Octave or similar tool knowledge.

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